Halide-To-Hardware Test Status
design-cpu-int-pointwise-SEED=1PASSED design-coreir-int-pointwise-SEED=1PASSED
design-cpu-int-pointwise-SEED=2PASSED design-coreir-int-pointwise-SEED=2PASSED
design-cpu-int-pointwise-SEED=3PASSED design-coreir-int-pointwise-SEED=3PASSED
design-cpu-int-pointwise-SEED=4PASSED design-coreir-int-pointwise-SEED=4PASSED
design-cpu-int-pointwise-SEED=5PASSED design-coreir-int-pointwise-SEED=5PASSED
design-cpu-int-conv-SEED=1PASSED design-coreir-int-conv-SEED=1FAILED
design-cpu-int-conv-SEED=2FAILED design-coreir-int-conv-SEED=2FAILED
design-cpu-int-conv-SEED=3PASSED design-coreir-int-conv-SEED=3FAILED
design-cpu-int-conv-SEED=4PASSED design-coreir-int-conv-SEED=4PASSED
design-cpu-int-conv-SEED=5PASSED design-coreir-int-conv-SEED=5FAILED
design-cpu-int-conv-SEED=6PASSED design-coreir-int-conv-SEED=6PASSED
design-cpu-int-conv-SEED=7PASSED design-coreir-int-conv-SEED=7PASSED
design-cpu-int-conv-SEED=8PASSED design-coreir-int-conv-SEED=8FAILED
design-cpu-int-conv-SEED=9PASSED design-coreir-int-conv-SEED=9FAILED
design-cpu-int-conv-SEED=10PASSED design-coreir-int-conv-SEED=10FAILED
design-cpu-int-conv-SEED=11PASSED design-coreir-int-conv-SEED=11FAILED
design-cpu-int-conv-SEED=12PASSED design-coreir-int-conv-SEED=12PASSED
design-cpu-int-conv-SEED=13PASSED design-coreir-int-conv-SEED=13FAILED
design-cpu-int-conv-SEED=14PASSED design-coreir-int-conv-SEED=14PASSED
design-cpu-int-conv-SEED=15PASSED design-coreir-int-conv-SEED=15FAILED
design-cpu-int-up-SEED=1PASSED design-coreir-int-up-SEED=1FAILED
design-cpu-int-up-SEED=2PASSED design-coreir-int-up-SEED=2FAILED
design-cpu-int-up-SEED=3PASSED design-coreir-int-up-SEED=3FAILED
design-cpu-int-up-SEED=4PASSED design-coreir-int-up-SEED=4PASSED
design-cpu-int-up-SEED=5PASSED design-coreir-int-up-SEED=5FAILED
design-cpu-int-down-SEED=1PASSED design-coreir-int-down-SEED=1FAILED
design-cpu-int-down-SEED=2FAILED design-coreir-int-down-SEED=2FAILED
design-cpu-int-down-SEED=3PASSED design-coreir-int-down-SEED=3FAILED
design-cpu-int-down-SEED=4PASSED design-coreir-int-down-SEED=4PASSED
design-cpu-int-down-SEED=5PASSED design-coreir-int-down-SEED=5FAILED
design-cpu-int-hist-SEED=1PASSED design-coreir-int-hist-SEED=1FAILED
design-cpu-int-hist-SEED=2PASSED design-coreir-int-hist-SEED=2FAILED
design-cpu-int-hist-SEED=3PASSED design-coreir-int-hist-SEED=3FAILED
design-cpu-int-hist-SEED=4PASSED design-coreir-int-hist-SEED=4PASSED
design-cpu-int-hist-SEED=5PASSED design-coreir-int-hist-SEED=5FAILED
design-cpu-int-total-SEED=1PASSED design-coreir-int-total-SEED=1FAILED
design-cpu-int-total-SEED=2PASSED design-coreir-int-total-SEED=2FAILED
design-cpu-int-total-SEED=3PASSED design-coreir-int-total-SEED=3FAILED
design-cpu-int-total-SEED=4PASSED design-coreir-int-total-SEED=4FAILED
design-cpu-int-total-SEED=5PASSED design-coreir-int-total-SEED=5FAILED
design-cpu-int-total-SEED=6PASSED design-coreir-int-total-SEED=6FAILED
design-cpu-int-total-SEED=7PASSED design-coreir-int-total-SEED=7FAILED
design-cpu-int-total-SEED=8PASSED design-coreir-int-total-SEED=8FAILED
design-cpu-int-total-SEED=9PASSED design-coreir-int-total-SEED=9FAILED
design-cpu-int-total-SEED=10PASSED design-coreir-int-total-SEED=10FAILED
design-cpu-int-total-SEED=11PASSED design-coreir-int-total-SEED=11FAILED
design-cpu-int-total-SEED=12FAILED design-coreir-int-total-SEED=12FAILED
design-cpu-int-total-SEED=13PASSED design-coreir-int-total-SEED=13FAILED
design-cpu-int-total-SEED=14PASSED design-coreir-int-total-SEED=14FAILED
design-cpu-int-total-SEED=15PASSED design-coreir-int-total-SEED=15FAILED
design-cpu-float-pointwise-SEED=1PASSED design-coreir-float-pointwise-SEED=1FAILED
design-cpu-float-pointwise-SEED=2PASSED design-coreir-float-pointwise-SEED=2FAILED
design-cpu-float-pointwise-SEED=3PASSED design-coreir-float-pointwise-SEED=3FAILED
design-cpu-float-pointwise-SEED=4PASSED design-coreir-float-pointwise-SEED=4FAILED
design-cpu-float-pointwise-SEED=5PASSED design-coreir-float-pointwise-SEED=5FAILED
design-cpu-float-conv-SEED=1PASSED design-coreir-float-conv-SEED=1FAILED
design-cpu-float-conv-SEED=2PASSED design-coreir-float-conv-SEED=2FAILED
design-cpu-float-conv-SEED=3PASSED design-coreir-float-conv-SEED=3FAILED
design-cpu-float-conv-SEED=4PASSED design-coreir-float-conv-SEED=4FAILED
design-cpu-float-conv-SEED=5PASSED design-coreir-float-conv-SEED=5FAILED
design-cpu-float-conv-SEED=6PASSED design-coreir-float-conv-SEED=6FAILED
design-cpu-float-conv-SEED=7PASSED design-coreir-float-conv-SEED=7FAILED
design-cpu-float-conv-SEED=8PASSED design-coreir-float-conv-SEED=8FAILED
design-cpu-float-conv-SEED=9PASSED design-coreir-float-conv-SEED=9FAILED
design-cpu-float-conv-SEED=10PASSED design-coreir-float-conv-SEED=10FAILED
design-cpu-float-conv-SEED=11PASSED design-coreir-float-conv-SEED=11FAILED
design-cpu-float-conv-SEED=12PASSED design-coreir-float-conv-SEED=12FAILED
design-cpu-float-conv-SEED=13PASSED design-coreir-float-conv-SEED=13FAILED
design-cpu-float-conv-SEED=14PASSED design-coreir-float-conv-SEED=14FAILED
design-cpu-float-conv-SEED=15PASSED design-coreir-float-conv-SEED=15FAILED
design-cpu-float-up-SEED=1PASSED design-coreir-float-up-SEED=1FAILED
design-cpu-float-up-SEED=2PASSED design-coreir-float-up-SEED=2FAILED
design-cpu-float-up-SEED=3PASSED design-coreir-float-up-SEED=3FAILED
design-cpu-float-up-SEED=4PASSED design-coreir-float-up-SEED=4FAILED
design-cpu-float-up-SEED=5PASSED design-coreir-float-up-SEED=5FAILED
design-cpu-float-down-SEED=1PASSED design-coreir-float-down-SEED=1FAILED
design-cpu-float-down-SEED=2PASSED design-coreir-float-down-SEED=2FAILED
design-cpu-float-down-SEED=3PASSED design-coreir-float-down-SEED=3FAILED
design-cpu-float-down-SEED=4PASSED design-coreir-float-down-SEED=4FAILED
design-cpu-float-down-SEED=5PASSED design-coreir-float-down-SEED=5FAILED
design-cpu-float-hist-SEED=1PASSED design-coreir-float-hist-SEED=1FAILED
design-cpu-float-hist-SEED=2PASSED design-coreir-float-hist-SEED=2FAILED
design-cpu-float-hist-SEED=3PASSED design-coreir-float-hist-SEED=3FAILED
design-cpu-float-hist-SEED=4PASSED design-coreir-float-hist-SEED=4FAILED
design-cpu-float-hist-SEED=5PASSED design-coreir-float-hist-SEED=5FAILED
design-cpu-float-total-SEED=1PASSED design-coreir-float-total-SEED=1FAILED
design-cpu-float-total-SEED=2PASSED design-coreir-float-total-SEED=2FAILED
design-cpu-float-total-SEED=3PASSED design-coreir-float-total-SEED=3FAILED
design-cpu-float-total-SEED=4PASSED design-coreir-float-total-SEED=4FAILED
design-cpu-float-total-SEED=5PASSED design-coreir-float-total-SEED=5FAILED
design-cpu-float-total-SEED=6PASSED design-coreir-float-total-SEED=6FAILED
design-cpu-float-total-SEED=7PASSED design-coreir-float-total-SEED=7FAILED
design-cpu-float-total-SEED=8PASSED design-coreir-float-total-SEED=8FAILED
design-cpu-float-total-SEED=9PASSED design-coreir-float-total-SEED=9FAILED
design-cpu-float-total-SEED=10PASSED design-coreir-float-total-SEED=10FAILED
design-cpu-float-total-SEED=11PASSED design-coreir-float-total-SEED=11FAILED
design-cpu-float-total-SEED=12PASSED design-coreir-float-total-SEED=12FAILED
design-cpu-float-total-SEED=13PASSED design-coreir-float-total-SEED=13FAILED
design-cpu-float-total-SEED=14PASSED design-coreir-float-total-SEED=14FAILED
design-cpu-float-total-SEED=15PASSED design-coreir-float-total-SEED=15FAILED